1. Field of the Invention
The present invention generally relates to a non-volatile memory device. More particularly, the present invention relates to a non-volatile memory device having a data retrieval function to compare applied retrieval data with storage data in order to determine whether or not the retrieval data matches the storage data.
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device has attracted attention as a new-generation non-volatile memory device. The MRAM device is a non-volatile memory device capable of non-volatile data storage using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit and also capable of random access to each thin film magnetic element.
In particular, recent announcement shows that the use of thin film magnetic elements having a magnetic tunnel junction (MTJ) as memory cells significantly improves performance of the MRAM device. The MRAM device including memory cells having a magnetic tunnel junction is disclosed in technical documents such as “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, February 2000, “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, February 2000, and “A 256 kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM”, ISSCC Digest of Technical Papers, TA7.6, February 2001.
FIG. 21 schematically shows the structure of a memory cell having a magnetic tunnel junction (hereinafter, sometimes simply referred to as “MTJ memory cell”).
Referring to FIG. 21, the MTJ memory cell includes a tunneling magneto-resistance element TMR and an access transistor ATR. Tunneling magneto-resistance element TMR has an electric resistance varying according to a magnetically written storage data level. Access transistor ATR is connected in series with tunneling magneto-resistance element TMR between a bit line BL and a source line SL. Typically, a field effect transistor formed on a semiconductor substrate is used as access transistor ATR.
A bit line BL, a write digit line WDL, a word line WL and a source line SL are provided for the MTJ memory cell. Bit line BL and write digit line WDL allow data write currents of different directions to flow therethrough in data write operation, respectively. Word line WL is used to conduct data read operation. Source line SL pulls down tunneling magneto-resistance element TMR to a ground voltage GND in data read operation. In data read operation, tunneling magneto-resistance element TMR is electrically coupled between source line SL and bit line BL in response to turning-ON of access transistor ATR.
FIG. 22 is a conceptual diagram illustrating data write operation to the MTJ memory cell.
Referring to FIG. 22, tunneling magneto-resistance element TMR has a ferromagnetic material layer FL having a fixed magnetization direction (hereinafter, sometimes simply referred to as “fixed magnetic layer”), and a ferromagnetic material layer VL that is magnetized in the direction corresponding to an external magnetic field (hereinafter, sometimes simply referred to as “free magnetic layer”). A tunneling barrier (tunneling film) TB is formed between fixed magnetic layer FL and free magnetic layer VL. Tunneling barrier TB is formed from an insulator film. Free magnetic layer VL is magnetized either in the same direction as or in the opposite direction to that of fixed magnetic layer FL according to a write data level. Fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL form a magnetic tunnel junction.
The electric resistance of tunneling magneto-resistance element TMR varies according to the relation between the respective magnetization directions of fixed magnetic layer FL and free magnetic layer VL. More specifically, the electric resistance of tunneling magneto-resistance element TMR has a minimum value Rmin when fixed magnetic layer FL and free magnetic layer VL have the same (parallel) magnetization direction, and has a maximum value Rmax when they have opposite (antiparallel) magnetization directions.
In data write operation, word line WL is inactivated and access transistor ATR is turned OFF. In this state, a data write current for magnetizing free magnetic layer VL is applied to each of bit line BL and write digit line WDL in a direction corresponding to the write data level.
FIG. 23 is a conceptual diagram showing the relation between the data write current and the magnetization direction of the tunneling magneto-resistance element in data write operation.
Referring to FIG. 23, the abscissa H(EA) indicates a magnetic field which is applied to free magnetic layer VL of tunneling magneto-resistance element TMR in the easy-axis (EA) direction. The ordinate H(HA) indicates a magnetic field which is applied to free magnetic layer VL in the hard-axis (HA) direction. Magnetic fields H(EA), H(HA) respectively correspond to two magnetic fields produced by the currents flowing through bit line BL and write digit line WDL.
In the MTJ memory cell, fixed magnetic layer FL is magnetized in the fixed direction along the easy axis of free magnetic layer VL. Free magnetic layer VL is magnetized either in the direction parallel or antiparallel (opposite) to that of fixed magnetic layer FL along the easy axis according to the storage data level (“1” and “0”). The MTJ memory cell is thus capable of storing one-bit data (“1” and “0”) according to the two magnetization directions of free magnetic layer VL.
The magnetization direction of free magnetic layer VL can be rewritten only when the sum of the applied magnetic fields H(EA) and H(HA) reaches the region outside the asteroid characteristic line in FIG. 23. In other words, the magnetization direction of free magnetic layer VL does not change if the strength of an applied data write magnetic field corresponds to the region inside the asteroid characteristic line.
As shown by the asteroid characteristic line, applying a magnetic field of the hard-axis direction to free magnetic layer VL enables reduction in a magnetization threshold value required to change the magnetization direction along the easy axis. When the operation point of data write operation is designed as in the example of FIG. 23, a data write magnetic field of the easy-axis direction is designed to have a strength HWR in the MTJ memory cell to be written. In other words, a data write current to be applied to bit line BL or write digit line WDL is designed to produce the data write magnetic field HWR. In general, data write magnetic field HWR is given by the sum of a switching magnetic field HSW required to switch the magnetization direction and a margin ΔH. Data write magnetic field HWR is thus given by HWR=HSW+ΔH.
In order to rewrite the storage data of the MTJ memory cell; that is, the magnetization direction of tunneling magneto-resistance element TMR, a data write current of a predetermined level or more must be applied to both write digit line WDL and bit line BL. Free magnetic layer VL in tunneling magneto-resistance element TMR is thus magnetized in the direction parallel or opposite (antiparallel) to that of fixed magnetic layer FL according to the direction of the data write magnetic field along the easy axis (EA). The magnetization direction written to tunneling magneto-resistance element TMR, i.e., the storage data of the MTJ memory cell, is held in a non-volatile manner until another data write operation is conducted.
FIG. 24 is a conceptual diagram illustrating data read operation from the MTJ memory cell.
Referring to FIG. 24, in data read operation, access transistor ATR is turned ON in response to activation of word line WL. As a result, tunneling magneto-resistance element TMR is pulled down to ground voltage GND and electrically coupled to bit line BL.
If bit line BL is then pulled up to a predetermined voltage, a memory cell current Icell corresponding to the electric resistance of tunneling magneto-resistance element TMR, that is, the storage data level of the MTJ memory cell, flows through a current path including bit line BL and tunneling magneto-resistance element TMR. For example, the storage data can be read from the MTJ memory cell by comparing memory cell current Icell with a predetermined reference current.
A data read current flows through tunneling magneto-resistance element TMR in data read operation. However, data read current Is is commonly set to a value that is about one to two orders smaller than the above data write current. Therefore, it is less likely that the storage data in the MTJ memory cell is erroneously rewritten due to the data read current Is in data read operation. In other words, non-destructive data read operation is possible.
FIG. 25 shows the structure of an MTJ memory cell formed on a semiconductor substrate.
Referring to FIG. 25, an access transistor ATR formed on a semiconductor main substrate SUB has impurity regions (n-type regions) 310, 320 and a gate 330. Impurity region 310 is electrically coupled to a source line SL through a metal film formed in a contact hole 341.
A write digit line WDL is formed in a metal wiring layer provided above source line SL. A tunneling magneto-resistance element TMR is provided above write digit line WDL. Tunneling magneto-resistance element TMR is electrically coupled to impurity region 320 of access transistor ATR through a strap 350 and a metal film formed in a contact hole 340. Strap 350 is formed from a conductive material, and is provided in order to electrically couple tunneling magneto-resistance element TMR to access transistor ATR. A bit line BL is provided above tunneling magneto-resistance element TMR and is electrically coupled to tunneling magneto-resistance element TMR.
Bit line BL receiving a data write current and a data read current and write digit line WDL receiving a data write current are formed using a metal wiring layer. Word line WL is provided in order to control the gate voltage of access transistor ATR. Therefore, it is not necessary to actively supply a current to word line WL. For improved integration, word line WL is commonly formed without using an additional independent metal wiring layer. In other words, word line WL is commonly formed in the same wiring layer as that of gate 330 by using a polysilicon layer or a polycide layer.
The MRAM device is thus capable of storing data in a non-volatile manner by using MTJ memory cells integrated on the semiconductor substrate. In each MTJ memory cell, the electric resistance of tunneling magneto-resistance element TMR varies according to the magnetization direction that is rewritable by an applied data write magnetic field. Accordingly, non-volatile data storage can be realized by using electric resistances Rmax, Rmin of tunneling magneto-resistance element TMR as the storage data levels (“1” and “0”).
An OUM (Ovonic Unified memory) cell increasingly attracts attention as a different type of non-volatile memory cell. The OUM is disclosed in, e.g., “Forefront of Non-Volatile Memory/The Future in Intel's Mind: From Flash Memory to OUM,” Nikkei Microdevices, March, 2002, pp. 65–78. The OUM cell is formed by a thin-film chalcogenide layer and a heat-generating element. Chalcogenide changes into an amorphous or crystalline state according to the heating pattern of the heat-generating element through which a data write current flows. The electric resistance of the chalcogenide layer varies between the amorphous state and the crystalline state. Therefore, non-volatile data storage can be implemented in the OUM cell by setting two supply patterns of the data write current (which correspond to two heating patterns for changing the chalcogenide layer into the amorphous and crystalline states, respectively) according to the write data level.
As described above, the MTJ memory cell is the same as the OUM cell in that current supply is required for data write operation and in that the electric resistance varies according to the storage data.
One of the main applications of the memory device is an associative memory which compares applied retrieval data with storage data in order to determine whether or not the retrieval data matches the storage data. At present, SRAM (Static Random Access Memory) cells based on a cross-coupled latch of the CMOS (Complementary Metal Oxide Semiconductor) structure are used in the associative memory. However, the SRAM cell has a large area. Moreover, the SRAM cell is a volatile memory in which the data stored therein is lost upon power-down. Therefore, the use of the SRAM cells is not always convenient.
It is also possible to use a commonly used non-volatile memory device, i.e., an EEPROM (Electrically Erasable/Programmable Read Only Memory) or a flash memory (R), in the associative memory. However, the EEPROM and the flash memory require a relatively long time for data write operation (program operation).